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CS4350
192 kHz Stereo DAC with Integrated PLL
Features
Advanced Multi-bit Delta-Sigma Architecture 109 dB Dynamic Range -91 dB THD+N 24-Bit Conversion Supports Audio Sample Rates Up to 192 kHz Low-Latency Digital Filtering Single-Ended or Differential Analog Output Architecture Integrated PLL Locks to Incoming Left-Right Clock - Eliminates the Need for External Masterclock Routing - Reduces Interference and Jitter Sensitivity - No External Loop Filter Components Required Automatic Sample-Rate Range Detection Popguard(R) Technology for Control of Clicks and Pops - Hardware Popguard Disable for Fast Startups Supports All Standard Serial Audio Formats Including Time-Division Multiplexed (TDM) +1.5 V to 5.0 V Logic Supplies for Serial Port +3.3 V to 5.0 V Control Port Interface
Control Port Mode Features
SPITM and IC(R) Modes ATAPI Mixing Mute Control for Individual Channels Digital Volume Control with Soft Ramp - 127.5 dB Attenuation - 1/2 dB Step Size - Zero Crossing Click-Free Transitions
3.3 V to 5.0 V
3.3 V to 5.0 V Level Translator Register/ Hardware Configuration Interpolation Filter with Volume Control Left Channel Output
Hardware or I2C/ SPI Control Data Reset
Multibit Modulator
DAC
Amp + Filter
1.5 V to 5.0 V Level Translator
PCM Serial Interface
Interpolation Filter with Volume Control RMCK
Multibit Modulator
DAC
Amp + Filter
Right Channel Output
Serial Audio Input LRCK Recovered MCLK
RMCK Phase Locked Loop
Internal Voltage Reference and Regulation
External Mute Control
Left and Right Mute Controls
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2007 (All Rights Reserved)
JULY '07 DS691F1
CS4350
Description
The CS4350 is a complete stereo digital-to-analog system including PLL-based master clock derivation, digital interpolation, 5th-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing, and analog filtering. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4350 supports all standard digital audio interface formats, including TDM. The CS4350 is available in a 24-pin TSSOP package in both Commercial (-40 to +85C) and Automotive grades (-40 to +105C). The CDB4350 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on page 40 for complete ordering information. These features are ideal for cost-sensitive, two-channel audio systems, including DVD players and recorders, settop boxes, digital TVs, mini-component systems, mixing consoles and automotive audio systems.
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TABLE OF CONTENTS
1. PIN DESCRIPTION.................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS....................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .......................................................................................... 8 ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ................................................................... 9 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) .................................................................. 10 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 12 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE.............................................................. 13 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT.................................................... 14 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT................................................... 15 DIGITAL CHARACTERISTICS .................................................................................................................. 16 POWER AND THERMAL CHARACTERISTICS........................................................................................ 16 3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 17 4. APPLICATIONS .................................................................................................................................... 18 4.1 Sample Rate Range and Oversampling Mode Detect................................................................... 18 4.1.1 Sample Rate Auto-Detect .................................................................................................... 18 4.2 System Clocking ............................................................................................................................ 18 4.2.1 Recovered Master Clock (RMCK)........................................................................................ 18 4.3 Digital Interface Format ................................................................................................................. 19 4.3.1 Time-Division Multiplex (TDM) Mode ................................................................................... 20 4.4 De-Emphasis ................................................................................................................................. 21 4.5 Mute Control .................................................................................................................................. 21 4.6 Recommended Power-Up Sequence ............................................................................................ 21 4.6.1 Stand-Alone Mode ............................................................................................................... 21 4.6.2 Control Port Mode ................................................................................................................ 22 4.7 Popguard Transient Control .......................................................................................................... 22 4.7.1 Power-Up ............................................................................................................................. 22 4.7.2 Power-Down......................................................................................................................... 22 4.7.3 Discharge Time .................................................................................................................... 22 4.8 Analog Output and Filtering ........................................................................................................... 23 4.9 Grounding and Power Supply Arrangements ................................................................................ 23 4.9.1 Capacitor Placement............................................................................................................ 23 5. STAND-ALONE OPERATION............................................................................................................... 24 5.1 Serial Port Format Selection.......................................................................................................... 24 5.2 De-Emphasis Control .................................................................................................................... 24 5.3 Popguard Transient Control .......................................................................................................... 24 6. CONTROL PORT OPERATION ............................................................................................................ 25 6.1 MAP Auto Increment ..................................................................................................................... 25 6.2 IC Mode ........................................................................................................................................ 25 6.2.1 IC Write ............................................................................................................................... 25 6.2.2 IC Read............................................................................................................................... 25 6.3 SPI Mode ....................................................................................................................................... 26 6.3.1 SPI Write .............................................................................................................................. 26 6.3.2 SPI Read.............................................................................................................................. 27 6.4 Memory Address Pointer (MAP) ................................................................................................... 27 6.4.1 INCR (Auto Map Increment Enable) .................................................................................... 27 6.4.2 MAP (Memory Address Pointer) .......................................................................................... 27 7. REGISTER QUICK REFERENCE ......................................................................................................... 28 8. REGISTER DESCRIPTION ................................................................................................................... 29 8.1 Device and Revision ID - Register 01h.......................................................................................... 29 8.2 Mode Control - Register 02h ......................................................................................................... 29 8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 29 DS691F1 3
CS4350
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 30 8.2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 30 8.3 Volume Mixing and Inversion Control - Register 03h .................................................................... 30 8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 30 8.3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 30 8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 31 8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 31 8.4 Mute Control - Register 04h ......................................................................................................... 32 8.4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 32 8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 32 8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3................................. 32 8.5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 33 8.6 Ramp and Filter Control - Register 07h ......................................................................................... 33 8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 33 8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 ............................................................. 34 8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 ........................................... 34 8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 34 8.7 Misc. Control - Register 08h .......................................................................................................... 34 8.7.1 Power Down (PDN) Bit 7...................................................................................................... 34 8.7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 35 8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 35 8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2 ......................................................................... 35 8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 35 9. FILTER PLOTS .................................................................................................................................. 36 10. PARAMETER DEFINITIONS............................................................................................................... 38 11. PACKAGE DIMENSIONS ................................................................................................................... 39 THERMAL CHARACTERISTICS ............................................................................................................... 39 12. ORDERING INFORMATION ............................................................................................................... 40 13. REVISION HISTORY .......................................................................................................................... 40
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LIST OF FIGURES
Figure 1. Equivalent Output Load .............................................................................................................. 11 Figure 2. Maximum Loading....................................................................................................................... 11 Figure 3. THD+N vs Output Amplitude for VA = 5.0 V ............................................................................... 11 Figure 4. THD+N vs Output Amplitude for VA = 3.3 V ............................................................................... 11 Figure 5. THD+N vs Output Amplitude for VA = 3.14 V ............................................................................. 11 Figure 6. Serial Port Timing, Non-TDM Mode............................................................................................ 14 Figure 7. Serial Port Timing, TDM Mode.................................................................................................... 14 Figure 8. Control Port Timing - IC Format................................................................................................. 14 Figure 9. Control Port Timing - SPI Mode .................................................................................................. 15 Figure 10. Typical Connection Diagram..................................................................................................... 17 Figure 11. Left-Justified up to 24-Bit Data.................................................................................................. 19 Figure 12. IS, up to 24-Bit Data ................................................................................................................ 19 Figure 13. Right-Justified Data................................................................................................................... 19 Figure 14. TDM Mode Connection Diagram .............................................................................................. 20 Figure 15. TDM Mode Timing .................................................................................................................... 20 Figure 16. De-Emphasis Curve.................................................................................................................. 21 Figure 17. Differential to Single-Ended Output Filter ................................................................................. 23 Figure 18. Passive Single-Ended Output Filter .......................................................................................... 23 Figure 19. Control Port Timing, IC Mode .................................................................................................. 26 Figure 20. Control Port Timing, SPI Mode ................................................................................................. 27 Figure 21. De-Emphasis Curve.................................................................................................................. 30 Figure 22. ATAPI Block Diagram ............................................................................................................... 31 Figure 23. Stopband Rejection (fast), all Modes ........................................................................................ 36 Figure 24. Stopband Rejection (slow), all Modes....................................................................................... 36 Figure 25. Single-Speed (fast) Passband Detail ........................................................................................ 36 Figure 26. Single-Speed (slow) Passband Detail....................................................................................... 36 Figure 27. Double-Speed (fast) Passband Detail....................................................................................... 36 Figure 28. Double-Speed (slow) Passband Detail ..................................................................................... 36 Figure 29. Quad-Speed (fast) Passband Detail ......................................................................................... 37 Figure 30. Quad-Speed (slow) Passband Detail........................................................................................ 37
LIST OF TABLES
Table 1. CS4350 Auto-Detect .................................................................................................................... 18 Table 2. Digital Interface Format - Stand-Alone Mode............................................................................... 24 Table 3. Digital Interface Formats .............................................................................................................. 29 Table 4. ATAPI Decode ............................................................................................................................. 31 Table 5. Example Digital Volume Settings ................................................................................................. 33
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CS4350 1. PIN DESCRIPTION
DIF2(AD1/CDOUT) DEM(AD0/CS) DIF0(SDA/CDIN) DIF1(SCL/CCLK) VLC VD_FILT GND RMCK VLS SCLK SDIN LRCK
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
RST AOUTBAOUTB+ BMUTEC VQ GND VA VBIAS+ AMUTEC AOUTA+ AOUTATSTO
Pin Name
VLC VD_FILT GND RMCK VLS SCLK SDIN LRCK TSTO AOUTA+,AOUTB+,AMUTEC BMUTEC VBIAS VA VQ
#
5 6 8 9 10 11 12 13
Pin Description
Control Interface Power (Input) - Positive power for the hardware/software control interface Regulator Voltage (Output) - Filter connection for internal voltage regulator Recovered Master Clock (Output) - Outputs a master clock derived from LRCK Serial Audio Interface Power (Input) - Positive power for the serial audio interface Serial Clock (Input) - Serial bit-clock for the serial audio interface Serial Audio Data Input (Input) - Input for two's complement serial audio data Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line Test Output - These pins need to be floating and not connected to any trace or plane.
7, 19 Ground (Input) - Ground reference
14, 15, Differential Analog Outputs (Output) - The full scale differential output level is specified in "DAC Ana22, 23 log Characteristics - Commercial (-CZZ)" on page 9. 16, 21 Mute Control (Output) - Control signals for optional mute circuit. 17 18 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC Analog Power (Input) - Positive power supply for the analog section Quiescent Voltage (Output) - Filter connection for internal quiescent voltage
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RST 24 Reset (Input) - When pulled low, device will power down and reset all internal registers to their default settings. Address Bit 1 / Serial Control Data Out (I/O) - Chip address bit 1 in IC Mode or data output in SPI Mode Address Bit 0 / Chip Select (Input) - Chip address bit 0 in IC Mode or Chip Select in SPI Mode Serial Control Data In (I/O) - Input/Output for IC data. Input for SPI data Serial Control Port Clock (Input) - Serial clock for the control port interface
Control Port Definitions AD1/CDOUT AD0/CS SDA/CDIN SCL/CCLK DIF0 DIF1 DIF2 DEM 1 2 3 4
Stand-Alone Definitions Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial 1, 3, 4 Clock, and Serial Audio Data 2 De-emphasis (Input) - Selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 kHz sample rates
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CS4350 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. Parameters
DC Power Supply Analog power Serial Audio Interface power Control Interface power Ambient Operating Temperature (Power Applied) Commercial (-CZZ) Automotive (-DZZ)
Symbol
VA VLS VLC TA TA
Min
4.75 3.14 1.35 3.14 -40 -40
Typ
5.0 3.3 3.3 3.3 -
Max
5.25 3.46 5.25 5.25 +85 +105
Units
V V V V C C
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.(Note 1) Parameters
DC Power Supply Analog power Serial Audio Interface power Control Interface power Input Current (Note 2) Digital Input Voltage Serial Audio Interface Control Interface Ambient Operating Temperature (power applied) Storage Temperature
Symbol
VA VLS VLC Iin VIN-LS VIN-LC TA Tstg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -55 -65
Max
6.0 6.0 6.0 10 VLS+ 0.4 VLC+ 0.4 125 150
Units
V V V mA V V C C
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies.
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CS4350 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ)
Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; TA = 25 C; Input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VD_FILT, VQ, VBIAS (as shown in the typical connection diagram in Figure 10) and output circuits as shown in Figure 17 and Figure 18; Fs = 48 kHz, 96 kHz, and 192 kHz; measurement bandwidth 10 Hz to 20 kHz. Parameter VA= 5.0 V
Dynamic Range (Note 3) 24-bit 16-bit A-Weighted unweighted A-Weighted unweighted 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB 98/106 95/103 98/106 95/103 2.61 5.22 VQ IOUTmax IQmax (Note 4) (Note 4) RL CL ZOUT -
Symbol
Min
Typ
101/109 98/106 95/96 92/93 -91 -78/-86 -38/-46 -90 -72/-73 -32/-33 101/109 98/106 95/96 92/93 -86 -91/-93 -78/-86 -38/-46 -83 -72/-73 -32/-33 100 0.1 -400 2.78 5.56 0.5*VA 10 100 3 100 100
Max
-86/-87 -35/-43 -77 -35/-43 0.25 2.96 5.92 -
Unit
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp Vpp VDC A A k pF
Single-ended/Differential
Total Harmonic Distortion + Noise (Note 3) 24-bit
16-bit
VA= 3.3 V
Dynamic Range (Note 3) 24-bit 16-bit A-Weighted unweighted A-Weighted unweighted 0 dB -2 dB -20 dB THD+N -60 dB 0 dB -20 dB -60 dB (1 kHz)
Single-ended/Differential
Total Harmonic Distortion + Noise (Note 3) 24-bit
16-bit
VA= 3.3 to 5.0 V
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch Gain Drift
Analog Output
Full Scale Output Voltage - Single Ended Full Scale Output Voltage - Differential Quiescent Voltage Max DC Current draw from an AOUT pin Max Current draw from VQ Max AC-Load Resistance Max Load Capacitance Output Impedance
Notes: 3. One-half LSB of triangular PDF dither is added to data 4. RL and CL represent the minimum resistance and maximum capacitance required for the CS4350's internal op-amp to remain stable. See Figure 1 and Figure 2 for more details.
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CS4350 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ)
Test conditions (unless otherwise specified): VLS = 1.35 V to 5.25 V, VLC = 3.14 V to 5.25 V, TA = -40 C to 105 C, input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT, VQ, VBIAS (as shown in the typical connection diagram in Figure 10) and output circuits as shown in Figure 17 and Figure 18; Fs = 48 kHz, 96 kHz, and 192 kHz; Measurement bandwidth 10 Hz to 20 kHz. Parameter VA= 4.75 V to 5.25 V
Dynamic Range (Note 3) 24-bit 16-bit A-Weighted unweighted A-Weighted unweighted 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB 95/103 92/100 94/103 91/100 2.55 5.10 VQ IOUTmax IQmax (Note 4) (Note 4) RL CL ZOUT -
Symbol
Min
Typ
101/109 98/106 95/96 92/93 -91 -78/-86 -38/-46 -90 -72/-73 -32/-33 101/109 98/106 95/96 92/93 -89 -91/-93 -78/-86 -38/-46 -83 -72/-73 -32/-33 100 0.1 -400 2.78 5.56 0.5*VA 10 100 3 100 100
Max
-85 -32/-40 -83 -31/-40 0.25 3.03 6.06 -
Unit
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp Vpp VDC A A k pF
Single-ended/Differential
Total Harmonic Distortion + Noise (Note 3) 24-bit
16-bit
VA= 3.14 V to 3.46 V
Dynamic Range (Note 3) 24-bit 16-bit A-Weighted unweighted A-Weighted unweighted -1 dB -2 dB -20 dB THD+N -60 dB 0 dB -20 dB -60 dB (1 kHz)
Single-ended/Differential
Total Harmonic Distortion + Noise (Note 5) 24-bit
16-bit
VA= 3.14 to 5.25 V
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch Gain Drift
Analog Output
Full Scale Output Voltage - Single Ended Full Scale Output Voltage - Differential Quiescent Voltage Max DC Current draw from an AOUT pin Max Current draw from VQ Max AC-Load Resistance Max Load Capacitance Output Impedance
Note:
5. One-half LSB of triangular PDF dither is added to data. Also, see Figure 3, Figure 4, and Figure 5 for more details on the CS4350-DZZ THD+N performance with 0dB input signal.
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125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
CS4350 AOUTx
3.3 F +
Analog Output
RL
CL
GND
2.5 3
5 10 15 20
Resistive Load -- RL (k )
Figure 1. Equivalent Output Load
Figure 2. Maximum Loading
Figures 3 through 5 show typical THD+N performance for CS4350 devices that exhibit the maximum full scale output voltages as specified in the DAC Analog Characteristics tables (see page 9 and 10). With decreasing VA, THD+N performance is increasingly affected by the full scale output voltage and temperature, with higher full scale output voltage and lower temperatures corresponding to lower THD+N performance.
-30 -40 -50 THD+N (dB) -60 -70 -80 -90 -100 0 TA = -40 C TA = 25 C TA = 85 C
-30 -40 -50 THD+N (dB) -60 -70 -80 -90 -100 0
TA = -40 C TA = 25 C TA = 85 C
-0.5
-1
-1.5 -2 Output Amplitude(dB)
-2.5
-3
-0.5
-1
-1.5 -2 Output Amplitude(dB)
-2.5
-3
Figure 3. THD+N vs Output Amplitude for VA = 5.0 V
Figure 4. THD+N vs Output Amplitude for VA = 3.3 V
-30 -40 -50 THD+N (dB) -60 -70 -80 -90 -100 0
TA = -40 C TA = 25 C TA = 85 C
-0.5
-1
-1.5 -2 Output Amplitude(dB)
-2.5
-3
Figure 5. THD+N vs Output Amplitude for VA = 3.14 V
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CS4350 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Amplitude vs. Frequency plots of this data are available in the "Filter Plots" on page 36. Parameter Fast Roll-Off
Passband (Note 6) -0.01 dB corner (Single Speed) -0.1 dB corner (Double Speed) -0.2 dB corner (Quad Speed) -3 dB corner (All Speed Modes) Frequency Response 10 Hz to 20 kHz StopBand Stop-Band Attenuation (Note 7) Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation De-emphasis Error (Note 8) (Relative to 1 kHz) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Single Speed Double Speed, Quad Speed 0 0 0 0 -0.01 -0.02 0.547 102 0 0 0 0 -0.01 -0.02 .583 64 Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz 9.4/Fs 6.5/Fs .454 .42 .27 .499 +0.01 +0.02 0.56/Fs 0 0.23 0.14 0.09 0.417 .37 .27 .499 +0.01 +0.02 0.14/Fs 0 0.23 0.14 0.09 Fs Fs Fs Fs dB dB Fs dB s s s dB dB dB Fs Fs Fs Fs dB dB Fs dB s s s dB dB dB
Min
Typ
Max
Unit
Slow Roll-Off (Note 9)
Passband (Note 6) -0.01 dB corner (Single Speed) -0.1 dB corner (Double Speed) -0.2 dB corner (Quad Speed) -3 dB corner (All Speed Modes) Frequency Response 10 Hz to 20 kHz StopBand Stop-Band Attenuation (Note 7) Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation De-emphasis Error (Note 8) (Relative to 1 kHz) Single Speed Double Speed, Quad Speed
Notes: 6. Response is clock dependent. 7. The Measurement Bandwidth is from stopband to 3 Fs. 8. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode. 9. Slow Roll-off interpolation filter is only available in Control Port Mode.
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CS4350 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Inputs: Logic 0 = GND; Logic 1 = VLS; CL = 20 pF. Parameters
RMCK Output Frequency (Note 10) RMCK Output Duty Cycle Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode LRCK Duty Cycle (Non-TDM Mode) SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge SCLK Frequency SCLK High Time SCLK Low Time Non-TDM Mode (refer to Figure 6) LRCK Edge to SCLK Rising Edge SCLK Rising Edge to LRCK Edge TDM Mode (refer to Figure 7) LRCK High Time SCLK Rising to LRCK Falling Edge LRCK Rising Edge to SCLK Rising Edge SCLK Frequency SCLK High Time SCLK Low Time Non-TDM Mode (refer to Figure 6) LRCK Edge to SCLK Rising Edge SCLK Rising Edge to LRCK Edge TDM Mode (refer to Figure 7) LRCK High Time SCLK Rising to LRCK Falling Edge LRCK Rising Edge to SCLK Rising Edge tlrckh tfsh tfss 25 8 1 ns ns ns tlcks tlckd 16 1 ns ns tsckh tsckl tlrckh tfsh tfss 6 3 1 11 11 27.7 ns ns ns MHz ns ns tlcks tlckd 11 1 ns ns tsckh tsckl tds tdh Fs
Symbol
Min
7.680 45 30 60 120 40 1 1 6 6
Max
55.3 55 54 108 216 60 55.3 -
Units
MHz % kHz % ns ns MHz ns ns
3.14 V VA 5.25 V and 1.35 V VLS 5.25 V
4.75 V VA 5.25 V and 3.14 V VLS 5.25 V
3.14 V VA < 4.75 V or 1.35 V VLS < 3.14 V
Note:
10. RMCK output frequency depends on the input LRCK frequency. See Section 4.1 and Section 4.2 for more details.
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CS4350
tlrckh
LRCK
(input)
tlckd
SCLK
(input)
tlcks
tsckh
tsckl
LRCK
(Input)
tfss
tfsh
tsckh
tsckl
SCLK
(Input)
tds
SDIN
(input)
tdh
MSB MSB-1
SDIN
(Input)
tds
tdh
MSB MSB-1
Figure 6. Serial Port Timing, Non-TDM Mode
Figure 7. Serial Port Timing, TDM Mode
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; CL = 20 pF. Parameter
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 11) SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
Symbol
fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 1000
Unit
kHz ns s s s s s s ns s ns s ns
Note:
11. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t Stop irs S tart
R e p e ate d S ta rt
t rd
t fd
Stop
SDA t buf t hdst t high t hdst t fc t susp
SCL t t t sud t ack t sust t rc
lo w
hdd
Figure 8. Control Port Timing - IC Format
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CS4350 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; CL = 20 pF. Parameter
CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling (Note 12) CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time (Note 13) Rise Time of CCLK and CDIN (Note 14) Fall Time of CCLK and CDIN (Note 14) Transition Time from CCLK to CDOUT Valid (Note 15) Time from CS rising to CDOUT High-Z
Symbol
fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 tscdov tcscdo
Min
500 500 1.0 20 66 66 40 15 -
Max
6 100 100 100 100
Unit
MHz ns ns s ns ns ns ns ns ns ns ns ns
Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For FSCK < 1 MHz. 15. CDOUT should not be sampled during this time.
RST
t srs
CS t spi t css CCLK t r2
CDIN
t scl
t sch
t csh
t f2
t dsu t dh
CDOUT
Hi-Impedance
t scdov
t scdov
t cscdo
Figure 9. Control Port Timing - SPI Mode
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CS4350 DIGITAL CHARACTERISTICS
Parameters
High-Level Input Voltage VLC or VLS = 5.0 V VLC or VLS = 3.3 V VLS = 2.5 V High-Level Input Voltage VLS = 1.5 V VLC or VLS = 5.0 V VLC or VLS = 3.3 V VLS = 2.5 V VLS = 1.5 V Input Leakage Current Input Capacitance High Level Output Voltage (RMCK) IO = 2 mA (VLS 3.0V) Low Level Output Voltage (RMCK) IO = -2 mA (VLS 3.0V) RMCK Output Load Drive Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage
Symbol
VIH VIH VIH VIH VIL VIL VIL VIL Iin VOH VOL
Min
0.7*VL 2.0 1.7 0.75*VL VLS-1.0 -
Typ
8 2 VA 0
Max
0.35*VL 0.8 0.7 0.25*VL 10 0.4 10 -
Units
V V V V V V V V A pF V V pF mA V V
VOH VOL
POWER AND THERMAL CHARACTERISTICS
Parameters
Power Supply Current - Normal Operation (Note 16) VA= 5.0 V VA= 3.3 V VLS = VLC =5.0 V (Note 17) VLS = VLC =3.3 V (Note 17) VLS = VLC = 5.0 V (Note 18) VLS = VLC = 3.3 V (Note 18) Power Supply Current - Power-Down State (Note 19) VA, VLS, VLC Power Dissipation - Normal Operation (Note 16) VA = VLC= VLS = 5.0 V VA = VLC= VLS = 3.3 V Power Dissipation - Power-Down State (Note 19) VA = VLC= VLS = 5.0 V VA = VLC= VLS = 3.3 V Power Supply Rejection Ratio (Note 20) (1 kHz) (60 Hz) Ipd 100 230 132 0.5 0.33 60 50 290 171 A mW mW mW mW dB dB
Symbol
IA IA ILS ILS ILC ILC
Min
-
Typ
28 24 4 2 14 14
Max
34 29 6 5 18 18
Units
mA mA mA mA mA mA
PSRR PSRR
Notes: 16. Current consumption increases with increasing Fs within the range of a speed mode. Variance between speed modes is small. Typ and Max values are based on Fs = 48 kHz. 17. ILS measured with no external loading on pin 7 (RMCK). 18. ILC measured with no external loading on pin 2 (SDA). 19. Power-down mode is defined as RST pin = Low with all clock and data lines held static. 20. Valid with the recommended capacitor values on VFILT, VQ, and VBIAS+ as shown in the typical connection diagram in Figure 10.
16
DS691F1
CS4350 3. TYPICAL CONNECTION DIAGRAM
+3.3 V or +5 V 0.1 F 18 *Optional for PopGuard Disable VLS *47 k 8 Digital Audio Source RMCK VD_FILT 6 0.1 F +
VA
+
10 F + 10 F
VBIAS+ 17
12 LRCK 10 SCLK 11 SDIN
10 F
+1.5 V to +5 V 0.1 F
9
VLS AMUTEC 16
CS4350
+3.3 V to +5 V 0.1 F 5 VLC
AOUTA+ 15 AOUTA- 14
Differential or Singleended Output Filter
AOUTA
BMUTEC 21 24 RST C/ Mode Configuration 4 DIF1(SCL/CCLK) 3 2 1 DIF0(SDA/CDIN) DEM(AD0/CS) DIF2(AD1/CDOUT) VQ 20
TS TO GN ND
AOUTB+ 22 AOUTB- 23
Differential or Singleended Output Filter
AOUTB
+ 3.3 F
D
13
7
N.C.
Figure 10. Typical Connection Diagram
DS691F1
G
19
17
CS4350 4. APPLICATIONS
4.1 Sample Rate Range and Oversampling Mode Detect
The device operates in one of three oversampling modes based on the input sample rate. In Control Port Mode, the allowed sample rate range in each mode will depend on how the FM[1:0] bits are configured. In Stand-Alone Mode, the sample rate range will be according to Table 1.
4.1.1
Sample Rate Auto-Detect
The Auto-Detect feature is enabled by default. In this state, the CS4350 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges shown in Table 1. Sample rates outside the specified range for each mode are not supported when Auto-Detect is enabled. Input Sample Rate (Fs)
30 kHz - 54 kHz 60 kHz - 108 kHz 120 kHz - 216 kHz Table 1. CS4350 Auto-Detect
Mode
Single-Speed Mode Double-Speed Mode Quad-Speed Mode
In Control Port Mode, the Auto-Detect feature can be disabled by the Functional Mode (FM[1:0]) bits in the control port register 02h. In this state, the CS4350 will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode must then be set manually according to one of the ranges referred to in Section 8.2.3. Sample rates outside the specified range for each mode are not supported. In Stand-Alone Mode it is not possible to disable auto-detect of sample rates.
4.2
System Clocking
The device requires external generation of the left/right (LRCK) and serial (SCLK) clocks. The left/right clock frequency is equal to the input sample rate (Fs). Refer to Section 4.3 for the required SCLK-to-LRCK timing associated with the selected digital interface format, and "Switching Specifications - Serial Audio Interface" on page 13 for the maximum allowed clock frequencies.
4.2.1
Recovered Master Clock (RMCK)
The CS4350 generates a high-frequency master clock (RMCK) which it derives from the LRCK input, available on the RMCK pin. In Stand-Alone Mode, the frequency of RMCK is equal to 256 x LRCK in Single-Speed and Double-Speed Mode; and 128 x LRCK in Quad-Speed Mode. In Control-Port Mode, the frequency of the RMCK signal can be selected through register 08h (see Section 8.7 on page 34 for more details).
18
DS691F1
CS4350
4.3 Digital Interface Format
The device will accept audio samples in 1 of 8 digital interface formats, as shown in Table 2 on page 24 for Stand-Alone Mode and Table 3 on page 29 for Control Port Mode. The desired serial audio interface format is selected via the DIF[2:0] bits in Control Port Mode (see Section 8.2.1), or the DIF[2:0] pins in Stand-Alone Mode (see Section 5.1). For illustrations of the required relationship between LRCK, SCLK and SDIN, see Figures 11-13. For all formats, SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to the Cirrus Logic Application Note AN282, The 2-Channel Serial Audio Interface: A Tutorial, available at www.cirrus.com.
LRCK Left Channel Right Channel
SCLK
SDIN
MSB
-1
-2
-3
-4
-5
+5
+4
+3
+2
+1
LSB
MSB
-1
-2
-3
-4
+5
+4
+3
+2
+1
LSB
Figure 11. Left-Justified up to 24-Bit Data
LRCK
Left Channel
Right Channel
SCLK
SDIN
MSB
-1
-2
-3
-4
-5
+5
+4
+3
+2
+1
LSB
MSB
-1
-2
-3
-4
+5
+4
+3
+2
+1
LSB
Figure 12. IS, up to 24-Bit Data
LRCK
Left Channel
Right Channel
SCLK
SDIN
LSB
MSB
-1
-2
-3
-4
-5
+7
+6
+5
+4
+3
+2
+1 LSB
MSB
-1
-2
-3
-4
-5
+7
+6
+5
+4
+3
+2
+1 LSB
Figure 13. Right-Justified Data
DS691F1
19
CS4350
4.3.1 Time-Division Multiplex (TDM) Mode
Four TDM interface modes are available that allow the CS4350 to input stereo PCM data in one of 4 time "slots". Figure 14 shows the serial port connections necessary to input 8-channel TDM data into four CS4350 devices, and the corresponding DIF[2:0] pin or register-bit settings required for each CS4350. Figure 15 shows the TDM data format for each of the four CS4350 devices shown in Figure 14. .
CS43501
DIF[2:0] = 100
CS43502
DIF[2:0] = 101
CS43503
DIF[2:0] = 110
CS43504
DIF[2:0] = 111
LRCK SCLK SDIN
ILRCK ISCLK SDIN
LRCK SCLK SDIN
LRCK SCLK SDIN
LRCK
SCLK TDM_OUT
TDM Source
Figure 14. TDM Mode Connection Diagram
256 clks LRCK SCLK SDIN1 MSB Slot 1, ch A 32 clks MSB Slot 1, ch B 32 clks MSB Slot 2, ch A 32 clks MSB Slot 2, ch B 32 clks MSB Slot 3, ch A 32 clks MSB Slot 3, ch B 32 clks MSB Slot 4, ch A 32 clks MSB Slot 4, ch B 32 clks
Data MSB LSB zero
Figure 15. TDM Mode Timing
20
DS691F1
CS4350
4.4 De-Emphasis
The device includes on-chip digital de-emphasis. Figure 16 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 16. De-Emphasis Curve
Note:
De-emphasis is only available in Single-Speed Mode.
4.5
Mute Control
The mute control pins (AMUTEC and BMUTEC) go active during power-up initialization, reset, muting (see Section 8.4.3), and loss of LRCK. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended single-supply system. Use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle-channel noise and signal-to-noise ratios which are only limited by the external mute circuit.
4.6 4.6.1
Recommended Power-Up Sequence Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are fixed to the appropriate frequencies, as discussed in Section 4.2. In this state, the control port registers are reset to their default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low power state with VQ low for approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). 3. The device will then initiate the power up sequence which lasts approximately 50 s when the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of power-up timing.
DS691F1
21
CS4350
4.6.2 Control Port Mode
1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate frequency, as discussed in Section 4.2. In this state, the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low-power state with VQ low. 3. Perform a control port write to a valid register prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 s when the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of power-up timing.
4.7
Popguard Transient Control
The CS4350 uses a novel technique to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
4.7.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients.
4.7.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.
4.7.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
22
DS691F1
CS4350
4.8 Analog Output and Filtering
The Cirrus Application Note titled Design Notes for a 2-Pole Filter with Differential Input, available as AN48 at www.cirrus.com, discusses the second-order Butterworth filter and differential-to-single-ended converter that was implemented on the CS4350 evaluation board, CDB4350. Figure 17 illustrates this implementation. If only single-ended outputs from the CS4350 are required, the passive output filter shown in Figure 18 can be used.
5600 pF 4.02 k 1000 pF 392 + C0G 22 F 562 47 k
CS4350 AOUTx AOUTx +
C0G 4.64 k
Analog Output
1.62 k .015 F
221
2700 pF C0G
GND
C0G
1.37 k
22 F
* See section 4.9 for ground connection details
Figure 17. Differential to Single-Ended Output Filter
CS4350
3.3 F
AOUTx +
+
560
Analog Output 2200 pF
10 k
GND * See section 4.9 for ground connection details
Figure 18. Passive Single-Ended Output Filter
4.9
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4350 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 10 shows the recommended power arrangements, with VA, VLC, and VLS connected to clean supplies. The use of split analog and digital ground planes is not recommended. However, if planes are split between digital ground and analog ground the GND pins of the CS4350 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the VBIAS, VFILT, and VQ pins in order to avoid unwanted coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Note: All decoupling capacitors should be referenced to GND.
The CDB4350 evaluation board demonstrates the optimum layout and power supply arrangements. DS691F1 23
CS4350 5. STAND-ALONE OPERATION
5.1 Serial Port Format Selection
The desired serial audio format is selected with the DIF2, DIF1 and DIF0 pins. For an explanation of the required relationship between the LRCK, SCLK and SDIN, see Figures 11-13. For all formats, SDIN is valid on the rising edge of SCLK. TDM Mode requires the selection of which stereo pair time "slot" is used to output data as shown in Table 2 and Figure 15. DIF2
0 0 0 0 1 1 1 1
DIF1
0 0 1 1 0 0 1 1
DIF0
0 1 0 1 0 1 0 1
DESCRIPTION Left-Justified, up to 24-bit data IS, up to 24-bit data Right-Justified, 16-bit data Right-Justified, 24-bit data TDM slot 0 TDM slot 1 TDM slot 2 TDM slot 3
FORMAT
0 1 2 3 4 5 6 7
FIGURE
12 11 13 13 15 15 15 15
Table 2. Digital Interface Format - Stand-Alone Mode
5.2
De-Emphasis Control
When pulled to VLC, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM pin turns off the de-emphasis filter.
5.3
Popguard Transient Control
In Stand-Alone Mode, Popguard is enabled by default. Popguard can be defeated in Stand-Alone Mode by placing a 47 k resistor between RMCK and VLS.
24
DS691F1
CS4350 6. CONTROL PORT OPERATION
The control port is used to load all the internal register settings (see "Register Description" on page 29). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port can operate in IC or SPI mode.
6.1
MAP Auto Increment
The device has a MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for consecutive writes or reads. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of consecutive registers.
6.2
IC Mode
In the IC Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 19 for the clock to data relationship). There is no CS pin. AD1 and AD0 enable the user to alter the chip address (10010[AD1][AD0][R/W]) and should be tied to VLC or GND as required before powering up the device. SPI Mode will be selected if the device ever detects a high to low transition on the AD0/CS pin after power-up.
6.2.1
IC Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in "Switching Characteristics - Control Port - IC Format" on page 14. 1. Initiate a START condition to the IC bus followed by the address byte. The upper 5 bits must be 10010. The sixth and seventh bit must match the settings of the AD1 and AD0 pins respectively, and the eighth must be 0 (the eighth bit of the address byte is the R/W bit). 2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.
6.2.2
IC Read
To read from the device, follow the procedure below while adhering to the control port switching specifications in "Switching Characteristics - Control Port - IC Format" on page 14. 1. Initiate a START condition to the IC bus followed by the address byte. The upper 5 bits must be 10010. The sixth and seventh bits must match the setting of the AD1 and AD0 pins, respectively, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the
DS691F1
25
CS4350
MAP or the default address (see Section 6.4.2) if an IC read is the first operation performed on the device. 3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read; then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the IC Write instructions, followed by step 1 of the IC Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS MAP BYTE INC 6 ACK START 5 4 3 2 1 0 ACK
7
DATA
6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1 0 0 1 0 AD1 AD0 R/W
ACK
ACK STOP
Figure 19. Control Port Timing, IC Mode
6.3
SPI Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 20 for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.
6.3.1
SPI Write
To write to the device, follow the procedure below while adhering to the control port switching specifications in "Switching Characteristics - Control Port - SPI Format" on page 15. 1. Bring CS low. 2. The address byte on the CDIN pin must then be 10011110 (R/W = 0). 3. Write to the memory address pointer, MAP. This byte points to the register to be written. 4. Write the desired data to the register pointed to by the MAP. 5. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high
26
DS691F1
CS4350
6.3.2 SPI Read
To read from the device, follow the procedure below while adhering to the values specified in "Switching Characteristics - Control Port - SPI Format" on page 15. 1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011111 (R/W = 1). 3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the SPI write operation. 4. If the INCR bit (see Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK to read from multiple consecutive registers. Bring CS high when reading is complete. 5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further reads from other registers are desired, bring CS high.
CS
CCLK C H IP ADDRESS CDIN 1001111 R/W MAP MSB b y te 1 CDOUT High Impedance DATA LSB b y te n MSB LSB MSB LSB C H IP ADDRESS 1001111 R/W
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 20. Control Port Timing, SPI Mode
6.4
Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
6.4.1
INCR (Auto Map Increment Enable)
Default = `0' 0 - Disabled 1 - Enabled
6.4.2
MAP (Memory Address Pointer)
Default = `0000'
DS691F1
27
CS4350 7. REGISTER QUICK REFERENCE
Addr
1h 2h 3h
Function
default Mode Control default Volume, Mixing, and Inversion Control default
7
1 Reserved 0 VOLB=A
6
1 DIF2 0 INVERTA
5
1 DIF1 0 INVERTB
4
1 DIF0 0 Reserved
3
DeviceID0 DEM1 0 ATAPI3
2
RevID2 DEM0 0 ATAPI2
1
RevID1 FM1 0 ATAPI1
0
RevID0 FM0 0 ATAPI0
Device and RevID DeviceID4 DeviceID3 DeviceID2 DeviceID1
0 AMUTE 1 VOL7 0 VOL7 0 SZC1 1 PDN 0
0 Reserved 0 VOL6 0 VOL6 0 SZC0 0 Reserved 0
0 MUTEC A=B 0 VOL5 0 VOL5 0 RMP_UP 1 FREEZE 0
0 MUTE_A 0 VOL4 0 VOL4 0 RMP_DN 1 POPG_EN 1
1 MUTE_B 0 VOL3 0 VOL3 0 Reserved 0 RMCK_ CTRL1 0
0 Reserved 0 VOL2 0 VOL2 0 FILT_SEL 0 RMCK_ CTRL0 0
0 Reserved 0 VOL1 0 VOL1 0 Reserved 0
1 Reserved 1 VOL0 0 VOL0 0 Reserved 1
4h
Mute Control default
5h
Channel A Volume Control default Channel B Volume Control default Ramp and Filter Control default
6h
7h
8h
Misc. Control default
R_ R_ SELECT1 SELECT0 0 0
28
DS691F1
CS4350 8. REGISTER DESCRIPTION
Note: All register access is Read/Write unless specified otherwise
8.1
Device and Revision ID - Register 01h
6 Device3 1 5 Device2 1 4 Device1 1 3 Device0 2 Rev2 1 Rev1 0 Rev0 -
7 Device4 1
Function: This register is Read-Only. It is decoded as follows: Rev
A B C2
Register 01h contents
1111,0000 1111,0001 1111,1111
8.2
Mode Control - Register 02h
6 DIF2 0 5 DIF1 0 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 FM1 0 0 FM0 0
7 Reserved 0
8.2.1
Digital Interface Format (DIF[2:0]) Bits 6-4
Function: These bits select the interface format for the serial audio input. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 11-13. DIF2
0 0 0 0 1 1 1 1
DIF1
0 0 1 1 0 0 1 1
DIF0
0 1 0 1 0 1 0 1
Description Left-Justified, up to 24-bit data IS, up to 24-bit data Right-Justified, 16-bit data Right-Justified, 24-bit data TDM slot 0 TDM slot 1 TDM slot 2 TDM slot 3
Table 3. Digital Interface Formats
Format 0 (Default)
1 2 3 4 5 6 7
Figure
11 12 13 13 15 15 15 15
DS691F1
29
CS4350
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2
Default = 0 00 - No De-emphasis 01 - 44.1 kHz De-emphasis 10 - 48 kHz De-emphasis 11 - 32 kHz De-emphasis Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (See Figure 21) Note: Mode De-emphasis is only available in Single-Speed
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 21. De-Emphasis Curve
8.2.3
Functional Mode (FM[1:0]) Bits 1-0
Default = 00 00 - Auto speed mode detect 01 - Single-Speed Mode (30 to 54 kHz sample rates) 10 - Double-Speed Mode (50 to 108 kHz sample rates) 11 - Quad-Speed Mode (100 to 216 kHz sample rates) Function: Selects the required range of input sample rates or auto speed mode.
8.3
Volume Mixing and Inversion Control - Register 03h
6 INVERT_A 0 5 INVERT_B 0 4 Reserved 0 3 ATAPI3 1 2 ATAPI2 0 1 ATAPI1 0 0 ATAPI0 1
7 VOLB=A 0
8.3.1
Channel A Volume = Channel B Volume (VOLB=A) Bit 7
Function: When set to 0 (default), the AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes. When set to 1, the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored.
8.3.2
Invert Signal Polarity (INVERT_A) Bit 6
Function: When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats.
30
DS691F1
CS4350
8.3.3 Invert Signal Polarity (INVERT_B) Bit 5
Function: When set to 1, this bit inverts the signal polarity of channel B. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats.
8.3.4
ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0
Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4350 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 4 and Figure 22 for additional information.
Left Channel Audio Data
A Channel Volume Control
MUTE
AoutA
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutB
Figure 22. ATAPI Block Diagram
ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
AOUTA MUTE MUTE MUTE MUTE aR aR aR aR
AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2]
Table 4. ATAPI Decode
DS691F1
31
CS4350
ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 AOUTA aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2]
Table 4. ATAPI Decode
8.4
Mute Control - Register 04h
6 Reserved 0 5 MUTEC A=B 0 4 MUTE_A 0 3 MUTE_B 0 2 Reserved 0 1 Reserved 0 0 Reserved 0
7 AMUTE 1
8.4.1
Auto-Mute (AMUTE) Bit 7
Function: When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0, this function is disabled
8.4.2
AMUTEC = BMUTEC (MUTEC A=B) Bit 5
Function: When set to 0 (default), the AMUTEC and BMUTEC pins operate independently. When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins go active only when the requirements for both AMUTEC and BMUTEC are valid.
8.4.3
Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3
Function: When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default), this function is disabled.
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CS4350
8.5 Channel A & B Volume Control - Register 05h & 06h
7 VOL7 0 6 VOL6 0 5 VOL5 0 4 VOL4 0 3 VOL3 0 2 VOL2 0 1 VOL1 0 0 VOL0 0
Digital Volume Control (VOL[7:0]) Bits 7-0 Default = 00h (0 dB) Function: The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments from 0 to -127.5 dB. Volume settings are decoded as shown in Table 5. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. Binary Code
00000000 00000001 00000110 11111111
Decimal Value
0 1 6 255
Volume Setting
0 dB -0.5 dB -3.0 dB -127.5 dB
Table 5. Example Digital Volume Settings
8.6
Ramp and Filter Control - Register 07h
7 SZC1 1 6 SZC0 0 5 RMP_UP 1 4 RMP_DN 1 3 Reserved 0 2 FILT_SEL 0 1 Reserved 0 0 Reserved 1
8.6.1
Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6
Default = 10 SZC1 SZC0
0 0 1 1 0 1 0 1
Description
Immediate Change Zero Cross Soft Ramp Soft Ramp on Zero Crossings
Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp PCM Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. DS691F1 33
CS4350
Soft Ramp and Zero Cross Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
8.6.2
Soft Volume Ramp-Up after Error (RMP_UP) Bit 5
Function: When set to 1 (default), an un-mute will be performed after executing a filter mode change, after LRCK is lost, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
8.6.3
Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4
Function: When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
8.6.4
Interpolation Filter Select (FILT_SEL) Bit 2
Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off. The specifications for each filter can be found in the "Combined Interpolation & On-Chip Analog Filter Response" on page 12, and response plots can be found in Figures 25 through 30.
8.7
Misc. Control - Register 08h
7 PDN 0 6 Reserved 0 5 FREEZE 0 4 POPG_EN 1 3 2 1 RMCK_CTRL1 RMCK_CTRL0 R_SELECT1 0 0 0 0 R_SELECT0 0
8.7.1
Power Down (PDN) Bit 7
Function: When set to 1 the entire device will enter a low-power state and the contents of the control registers will be retained. The power-down bit defaults to `0' on power-up.
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8.7.2 Freeze Controls (FREEZE) Bit 5
Function: When set to 1, this function allows modifications to be made to the registers without the changes taking effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. When set to 0 (default), register changes take effect immediately.
8.7.3
Popguard Enable (POPG_EN) Bit 4
Function: When set to 1, (default) the Device will initiate a ramping function as outlined in Section 4.7 on page 22. When set to 0, the outputs will step to VQ upon release of PDN.
8.7.4
RMCK control (RMCK_CTRL[1:0]) Bits 3:2
Default = 00 RMCK_CTRL1 RMCK_CTRL0
0 0 1 1 0 1 0 1
Mode
256x LRCK for 48 kHz and 96 kHz, 128x @ 192kHz 512x @ 48kHz, 256x @ 96 kHz, 128x @ 192kHz Manual control (see RMCK Ratio Select) RMCK pin driven low
Function: These bits set the function of the RMCK pin with respect to the LRCK.
8.7.5
RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1
Default = 00 Function: To select the RMCK-to-LRCK ratio. R_SELECT1
0 0 1 1
R_SELECT0
0 1 0 1
RMCK/LRCK Ratio
512 256 128 64
Note: RMCK_CTRL must be set to 10 to enable this function. Please note the maximum RMCK output frequency as specified in the "Switching Specifications - Serial Audio Interface" on page 13.
DS691F1
35
CS4350 9. FILTER PLOTS
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
Figure 23. Stopband Rejection (fast), all Modes
0.02
Figure 24. Stopband Rejection (slow), all Modes
0.02
0.015
0.015
0.01
0.01
0.005
Amplitude (dB)
0.005
Amplitude (dB)
0
0
0.005
0.005
0.01
0.01
0.015
0.015
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 25. Single-Speed (fast) Passband Detail
0.5
Figure 26. Single-Speed (slow) Passband Detail
0.5
0.4
0.4
0.3
0.3
0.2
0.2
Amplitude (dB)
Amplitude (dB)
0.1
0.1
0
0
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 27. Double-Speed (fast) Passband Detail
Figure 28. Double-Speed (slow) Passband Detail
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DS691F1
CS4350
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
Amplitude (dB)
0
Amplitude (dB)
0 0.05 0.1 0.15 0.2 Frequency (normalized to Fs) 0.25 0.3
0.1
0.1
0
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
0
0.05
0.1
0.15 0.2 Frequency (normalized to Fs)
0.25
0.3
Figure 29. Quad-Speed (fast) Passband Detail
Figure 30. Quad-Speed (slow) Passband Detail
DS691F1
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CS4350 10.PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. Then, 60 dB is added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/C. Intra-Channel Phase Deviation The deviation from linear phase within a given channel. Inter-Channel Phase Deviation The difference in phase between channels.
38
DS691F1
CS4350 11.PACKAGE DIMENSIONS 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1 SEATING PLANE A
E b2 SIDE VIEW
123
L
e
END VIEW
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8
MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. 1. D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
Parameters
Package Thermal Resistance Single-Layer PCB Multi-Layer PCB
Symbol
JA
Min
-
Typ
70 105
Max
-
Units
C/Watt
DS691F1
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CS4350 12.ORDERING INFORMATION
Product Description
192 kHz Stereo DAC with Integrated PLL
Package Pb-Free
Grade
Temp Range
Container
Rail Tape and Reel Rail Tape and Reel -
Order#
Commercial -40 to +85C 24-TSSOP YES Automotive -40 to +105C -
CS4350-CZZ CS4350-CZZR CS4350-DZZ CS4350-DZZR CDB4350
CS4350
CDB4350
Evaluation Board for CS4350
13.REVISION HISTORY
Release Changes -Changed description of TSTO pin in "Pin Description" on page 6 and "Typical Connection Diagram" on page 17. -Corrected Full-Scale Voltage in "RL and CL represent the minimum resistance and maximum capacitance required for the CS4350's internal op-amp to remain stable. See Figure 1 and Figure 2 for more details." on page 9. -Changed base address in "IC Mode" on page 25 and "SPI Mode" on page 26. -Corrected typographical error in chip address shown in Section 6.2 on page 25. -Corrected typographical error in value stated for the upper five bits in Section 6.2.1 on page 25. -Updated "DAC Analog Characteristics - Commercial (-CZZ)" on page 9. -Added "DAC Analog Characteristics - Automotive (-DZZ)" on page 10. -Updated "Switching Specifications - Serial Audio Interface" on page 13. -Updated "Power and Thermal Characteristics" on page 16. -Updated "DAC Analog Characteristics - Commercial (-CZZ)" on page 9. -Updated "DAC Analog Characteristics - Automotive (-DZZ)" on page 10. -Added Figure 3, Figure 4, and Figure 5 on page 11. -Updated "Switching Specifications - Serial Audio Interface" on page 13. -Updated "Digital Characteristics" on page 16.
A2
A3
PP1
F1
40
DS691F1
CS4350
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor SPI is a trademark of Motorola, Inc.
DS691F1
41

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